1 ) Field of the Invention
This invention relates generally to fabrication of semiconductor devices and more particularly to methods to form contact plugs and barrier layers and interconnects.
2 ) Description of the Prior Art
It is well known that integrated circuit fabrication on semiconductor wafers requires the formation of precisely controlled apertures, such as contact openings, that are subsequently filled with a conductive metal and interconnected to create components and very large scale integrated (VLSI) or ultra large scale integrated (ULSI) circuits. The methods for defining and forming such openings are equally well known to those who are skilled in the art. Market demands for faster and more powerful integrated circuits have resulted in significant growth in the number of devices per cm2, i.e., a higher packing fraction of active devices. This increased packing fraction invariably means that the interconnections for ever-more-complicated circuits are made to smaller dimensions than before. Thus the aspect ratios of the contacts, i.e., the ratio of the opening depth to the opening diameter, have increased.
In the past, aluminum (Al) was deposited in the contact openings over a barrier layer to form contacts. However, some fabrication processes, especially those used to produce CMOS and bipolar semiconductors, now use tungsten (W) deposited within the contact opening over an adhesion/barrier layer of titanium/titanium nitride (Ti/TiN). Such adhesion/barrier layers are needed because of the extremely poor adhesion of tungsten applied by chemical vapor deposition (CVD) on such dielectrics as borophosphosilicate glass (BPSG), silicon dioxide, thermal oxide, and plasma-enhanced oxide and silicon nitride. However, it is known that tungsten adheres well to TiN and that TiN adheres well to Ti and that Ti, in turn, adheres well to the dielectrics listed. Thus, a method that achieves good adhesion of CVD tungsten to the substrate is achieved by interposing layers of titanium and titanium nitride between the dielectric and the tungsten plug.
However, the prior art W plug processes can be improved upon.
The importance of overcoming the various deficiencies noted above is evidenced by the extensive technological development directed to the subject, as documented by the relevant patent and technical literature. The closest and apparently more relevant technical developments in the patent literature can be gleaned by considering the following.
U.S. Pat. No. 6,001,726: Method for using a conductive tungsten nitride etch stop layer to form conductive interconnects and tungsten nitride contact structure—forming a contact structure for a shallow junction device—Inventor: Nagabushnam, Rajan.
U.S. Pat. No. 6,573,147: Method of forming a semiconductor device having contact using crack-protecting layer—Formation of contact involves forming crack-protecting layer on interlayer dielectric layer—Inventor: Moon, Kwang-jin; Yongin,
US20030203512A1: METHOD FOR FABRICATING SEMICONDUCTOR MEMORY DEVICE—Manufacture of semiconductor memory device, e.g. dynamic random access memory, by sequentially forming insulating layer, contact hole, first diffusion barrier, conductive layer, and conductive plug in semiconductor substrate.
U.S. Pat. No. 5,913,143: Method of making a multilayer interconnection of semiconductor device using plug. Inventor: Harakawa, Hideaki.